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PIC18F2221/2321/4221/4321 FAMILY

DS39689F-page 42

2009 Microchip Technology Inc.

If the IRCF bits and the INTSRC bit are all clear, the

INTOSC output is not enabled and the IOFS bit will

remain clear; there will be no indication of the current

clock source. The INTRC source is providing the

device clocks.

If the IRCF bits are changed from all clear (thus,

enabling the INTOSC output) or if INTSRC is set, the

IOFS bit becomes set after the INTOSC output

becomes stable. Clocks to the device continue while

the INTOSC source stabilizes after an interval of

TIOBST (parameter 39, Table 27-10).

If the IRCF bits were previously at a non-zero value, or

if INTSRC was set before setting SCS1 and the

INTOSC source was already stable, the IOFS bit will

remain set.

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTOSC

multiplexer while the primary clock is started. When the

primary clock becomes ready, a clock switch to the

primary clock occurs (see Figure 4-4). When the clock

switch is complete, the IOFS bit is cleared, the OSTS

bit is set and the primary clock is providing the device

clock. The IDLEN and SCS bits are not affected by the

switch. The INTRC source will continue to run if either

the WDT or the Fail-Safe Clock Monitor is enabled.

FIGURE 4-3:

TRANSITION TIMING TO RC_RUN MODE

FIGURE 4-4:

TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

OSC1

Peripheral

Program

INTRC

Counter

Clock

CPU

Clock

PC + 2

123

n-1

Clock Transition(1)

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

Q3 Q4

OSC1

Peripheral

Program

INTOSC

PLL Clock

PC + 4

Output

CPU Clock

PC + 2

Clock

Counter

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 TOSC.

SCS<1:0> bits Changed

TPLL(1)

n-1 n

Clock

OSTS bit Set

Transition(2)

Multiplexer

TOST(1)

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